1. Field of the Invention
The present invention relates to forming planar and semi-planar insulator structures on semiconductor devices and more specifically to a chemical vapor deposition process that allows for simultaneous deposition and viscoelastic flow for semiconductor integrated fabrication.
2. Prior Art
Increasing demands on advanced very large scale integrated circuit (VLSI) metal-oxide semiconductor (MOS) devices in terms of numbers of functions and circuit speed require size reduction of circuit structures, as well as an increase in the number of conductor and insulator layers. Chemical vapor deposition (CVD) is a process which has developed in the semiconductor industry for manufacturing integrated and discrete semiconductor devices such as the above mentioned MOS devices.
In a typical manufacturing process a large (2-8 inch; 50-200 millimeter) wafer of silicon, germanium or similar material in extremely pure crystalline form is overlayed sequentially with numerous layers of material which function as conductors, semiconductors or insulators. Each subsequent layer is deposited and patterned usually by photolithographic techniques such that the sequence of layers forms a complex array of electronic circuitry. However, the multiple layers can be formed only with difficulty unless the substrate topography is planarized in an early stage of the manufacturing process and is then maintained as closely as possible to a planar surface throughout subsequent layer depositions.
Generally each device on the wafer is much smaller than the wafer itself. Once the wafer has been manufactured, one of the final steps in the manufacturing sequence is to cut the wafer along predetermined scribe lines to many individual devices which are commonly referred to as "chips." However, because the chips are so small and their circuitry is so complex, almost any flaw or irregularity in a layer can disrupt the circuit patterns and render a given chip useless. Indeed it is fairly common for a substantial percentage of the chips on a wafer to be found defective upon testing. For example, using a prior art technique of film deposition followed by thermal fusion flow to planarize a glass layer can cause voids or other layer inconsistencies.
Thermal fusion flow, used as a generic term for glass flow and glass reflow is generally performed on the pre-metal dielectric passivation layers used in typical metal-oxide semiconductor (MOS) fabrication sequences. The flow is used to densify the glass layer and prepare it for a subsequent contact hole etch, and at the same time to improve its step coverage properties. The topography-smoothing measure is intended to ensure the continuity of the overlying metallization (See Prior Art Reference No. 7).
Although the use of a thermal fusion flow process is fairly common to obtain smooth or planarized successive layers, the likelihood of voids and other inconsistencies in the layers and the temperatures necessary to achieve the flow can foreclose the application of the thermal fusion flow process to heat sensitive VLSI devices.
A typical CVD glass layer is generally comprised of approximately six to eight weight percent (6-8 wt %) phosphorus-containing phosphosilicate glass (PSG). The ability of PSG to undergo viscoelastic flow at a given temperature is primarily a function of the phosphorus content in the glass; however, temperatures necessary to achieve flow of the PSG layer, that is 1050.degree. C. to 1100.degree. C., preclude the use with heat sensitive VLSI devices. (See Prior Art Reference No. 6) However, the incorporation of boron into PSG to form a borophosphosilicate glass (BPSG) has made it possible to reduce the thermal fusion flow temperature by as much as 300.degree. C. without impairing the excellent properties of BPSG. In terms of stress and other properties, BPSG surpasses the standard PSG (See Prior Art Reference No. 5). Additionally, BPSG layers have been employed successfully as inner layer insulators for contour tapering and planarization of CMOS VLSI circuits (See Prior Art Reference No. 1).
The conventional method for BPSG processing consists of formation of the glass layer by CVD. CVD processes operate on the basis of two surface reaction steps. First, one or more reactive gases, from which the compound or elements to be deposited will be obtained, are passed over the surface of the wafer under reaction conditions at which the wafer surface will catalyze the liberation of the deposited materials. In some cases the reactive gas will be introduced directly into the reactor, while in others it will be formed "in situ" in the gas space in the reactor by reaction from other introduced gases.
The liberation reaction at the wafer surface may be a combination reaction in which two gases react to yield the deposit material and usually at least one gas as a by-product, or it may be a decomposition reaction in which a single reactive gas is decomposed to yield the deposit material and one or more by-product gases. The liberation reaction is followed by a second surface reaction in which the deposit material chemically combines with the surface of the wafer to form an integral bond and build up a layer or film of deposited material. For example, the BPSG deposition is normally done after the completion of high temperature processes such as epitaxy; oxidation; diffusion; refractory metal; metal silicide or polycide formation; or silicon nitride deposition on a device wafer. Deposition of BPSG is achieved by the co-oxidation of the hydride gases silicon hydride (SiH.sub.4), boron hydride (B.sub.2 H.sub.6) and phosphorus hydride (PH.sub.3) with O.sub.2 at atmospheric or a low pressure in the temperature range of 350.degree.-430.degree. C. (See Prior Art Reference No. 1 and 5).
Alternatively, oxygen assisted vapor pyrolysis of TEOS also known as tetraethylorthosilicate or tetraethoxysilane, with trimethylborate (TMB) as a boron source and phosphine as a phosphorus source, can be used at low pressure of 0.3-1 torr and in the temperature range of approximately 640.degree.-660.degree. C. (See Prior Art References No. 2, 3, 4 and 8). Typically CVD reaction conditions and reactor parameters must be within certain narrow limits if the necessary surface reaction conditions, necessary for formation of void-free uniform films are to be maintained and a satisfactory yield of uniform well bonded layers of the deposited materials obtained.
Due to numerous problems which can commonly occur during CVD processes or due to the size of the geometries of the wafer itself, a batch of wafers from a single reactor run may not have uniform thickness of the deposited layer over all the wafers. Prior Art Reference No. 3 describes some of the problems associated with prior art CVD processes. Additionally, some of the geometries may not be covered at all by the deposited glass layer. After the deposition of the glass layer, the coated devices are exposed to a sufficiently high temperature that is compatible with the thermal fusion flow of the deposited glass. After a time period long enough to cause the glass to soften viscoelastically, the desired effect of contour modification which can range from step tapering to partial or full planarization can be produced. Theoretically, the thermal fusion flow process is to remedy the inconsistencies of the deposited layer thickness and to fill and planarize the geometries on the wafer. However, because of the very low viscosity required, the partial or full planarization of the layer may be difficult to achieve by conventional techniques. The flow in a BPSG glass improves with higher temperatures until achieving a substantially planarized topography at approximately 950.degree. C. These techniques are described in Prior Art Reference No. 4.
The wafers are then patterned by photolithography and etching to form contact windows through the glass to the underlying conductor areas. In some cases, a second fusion known as reflow, is executed to round the edges of the openings in the glass. The structure is now ready for deposition of the next layer of conductor material that will result in a continuous layer of uniform thickness, a feature essential to the achievement of improved device yields and improved reliability.
An alternative process that can be used to produce a planarized structure is based on depositing a very thick (in terms of step heights) and extremely conformal layer of an insulator material, followed by reactive ion etching to reduce the thickness of the planarized insulator to an acceptable level. This method is cumbersome and slow, since it requires the deposition and etch back of thick layers. Worse, it is limited by the pattern aspect ratio, H/W, (step height/step-to-step spacing) of about 2.5, precluding its application to small pattern geometries.
However, a severe limitation of the conventional technology is the ability to produce a truly planarized insulator structure compatible with pattern features of advanced VLSI MOS circuits typically ranging from 1 or 2 microns to as small as 0.3 microns. An identified problem is that once the CVD layer starts to flow, there is the possibility that micron or sub-micron sized pattern features could be lost because the flowing layer would flow over the top of them as opposed to filling in the feature as desired. This identified problem is in addition to the danger of creating voids and other irregularities during the initial CVD deposition. An additional limitation of conventional technologies is that the wafers require additional handling. Generally, the wafers are subjected to at least two steps. First, there is the CVD deposition process within the reactor. Then the wafers are subjected to flow temperatures which may preclude the application of the thermal reflow process to heat sensitive VLSI devices.
Ideally, it would be advantageous to have a deposition/planarization process that would create and deposit a glass film of varying composition by CVD and simultaneously with the deposition flow the layer as to completely fill, without voids, all spaces and trenches between the micron and sub-micron pattern features. This approach would eliminate the difficult requirement of substantially perfect conformality that must be attained by other methods of film deposition if planarization is to be accomplished.
Further, it would be advantageous to be able to achieve these results at temperatures not exceeding the maximum of 950.degree. C. and preferably at or below 875.degree. C. so as to allow the processing of VLSI silicon devices such as complementary metal oxide semiconductor (CMOS) or erasable programmable read only memory (EPROM) devices.
Additionally, it would be advantageous if the glass layer could be synthesized by a fully controlled CVD process from organic or organometallic reactants whose toxicity levels are substantially lower than those of traditionally used hydrides.
A further advantage of using organic or organometallic reactants is that the chemical properties do not involve pyrophoricity and chemical instability during storage. Additional advantages include an increased efficiency for wafer handling and an improved cost efficiency since a greater wafer yield can be obtained.